Flash memory is a non-volatile memory (NVM) that is a specific type of electrically erasable programmable read-only memory (EEPROM). One commonly employed type of flash memory technology is NAND flash memory. NAND flash memory requires small chip area per cell and is typically divided into one or more banks or planes. Each bank is divided into blocks; each block is divided into pages. Each page includes a number of bytes for storing user data, error correction code (ECC) information, or both.
There are three basic operations for NAND devices: read, write and erase. The read and write operations are performed on a page-by-page basis. Page sizes are generally 2N bytes of user data (plus additional bytes for ECC information), where N is an integer, with typical user data page sizes of, for example, 2,048 bytes (2 KB), 4,096 bytes (4 KB), 8,192 bytes (8 KB) or more per page. A “read unit” is the smallest amount of data and corresponding ECC information that can be read from the NVM and corrected by the ECC, and might typically be between 4K bits and 32K bits (e.g., there is generally an integer number of read units per page). Pages are typically arranged in blocks, and an erase operation is performed on a block-by-block basis. Typical block sizes are, for example, 64, 128 or more pages per block. Pages must be written sequentially, usually from a low address to a high address within a block. Lower addresses cannot be rewritten until the block is erased. Associated with each page is a spare area (typically 100-640 bytes) generally used for storage of ECC information and/or other metadata used for memory management. The ECC information is generally employed to detect and correct errors in the user data stored in the page, and the metadata might be used for mapping logical addresses to and from physical addresses. In NAND flash chips with multiple banks, multi-bank operations might be supported that allow pages from each bank to be accessed substantially in parallel.
NAND flash memory stores information in an array of memory cells made from floating gate transistors. These transistors hold their voltage level, also referred to as charge, for long periods of time, on the order of months or years, without external power being supplied. In single-level cell (SLC) flash memory, each cell stores one bit of information. In multi-level cell (MLC) flash memory, each cell can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells. MLC NAND flash memory employs multiple voltage levels per cell with a serially linked transistor arrangement to allow more bits to be stored using the same number of transistors. Thus, considered individually, each cell has a particular stored (programmed) charge that corresponds to the logical bit value(s) being stored in the cell, and the cells are read based on one or more threshold voltages for each cell.
While, ideally, all cells in the NVM would have the same threshold voltages, in practice the threshold voltages differ across the cells in “threshold voltage distributions” that are similar in shape to a Gaussian probability curve. Considered across a large number of cells (e.g., a read unit or a page), there are as many threshold voltage distributions (e.g., Gaussian probability curves) as there are states per cell (e.g., 2b distributions per cell, where b is the number of bits). Thus, for SLC flash memories, there are two states (0 or 1) and thus two threshold voltage distributions (one for zeroes and another for ones) per cell, and a single read threshold voltage. Most MLC NAND flash memories employs four possible states per cell, and can thus store two bits of information per cell. Thus, for MLC flash memories, there are four states (e.g., 00, 01, 10, 11) and thus four threshold voltage distributions and three read thresholds.
Increasing the number of bits per cell causes cell-to-cell interference and retention noise (e.g., a drift in the stored charge, such as due to leakage) to become more severe, which reduces the amount of voltage margin separating each voltage level and increases the likelihood of read errors and, thus, the bit error ratio (BER) of the system. Further, the threshold voltage distributions of each cell can change over operating time of the NVM, for example due to read disturb, write disturb, retention loss, cell aging and process, voltage and temperature (PVT) variations, also increasing the BER. When a bit error is encountered in a read unit read from NVM, the system (e.g., a controller coupled to the NVM) might re-read the read unit at different voltage values of the read threshold to attempt to locate a sample of the read unit that is hard-decoding correctable. Further, software complexity might be increased to compensate for a larger BER, for example by employing an error correction code (ECC) such as Bose-Chaudhuri-Hocquenghem (BCH) and Low-Density Parity-Check (LDPC).
As memory devices become smaller and the number of levels per cell increases, more powerful ECC is required. For example, ECC is improved by decreasing the code rate for BCH codes, however, decreasing the code rate reduces the storage capacity of the NVM. Unlike BCH codes, LDPC codes allow soft-decision decoding, where in addition to estimating each bit value (“hard decoding”), the decoder also estimates each bit's reliability (“soft-decision decoding”) For LDPC codes to outperform BCH codes, improved estimation of each bit's reliability is desired.